[address-policy-wg] Re: Fallacy by Kurt (was Re: IPv6 Policy Clarification - Initial allocation criteria "d)")

Oliver Bartels:

>>So that would be a maximum of 10.000 routing table entries (if we
>>can manage to keep it at "1 prefix per LIR").
> 
> Full Ack.
> 
> A table of this size is handled with a one cycle memory access
> in modern routing hardware.

By definition of "one cycle memory access", any table of any size
can be handled with a one cycle memory access in any routing hardware.

However, memory access cycle can be a lot larger than a CPU clock
cycle.

On typical modern chips, tens of registers can be accessed within
a CPU cycle. On chip primary cache with thousands of entries
needs about twice or three times more than that. Off chip cache
needs about ten, twenty or, maybe, hundred more to access.

							Masataka Ohta